1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device preferable for an MOS transistor and the like.
2. Description of the Related Art
In a manufacturing process of silicon substrates and a manufacturing process of semiconductor devices, chemical solution treatment for dissolving surface layers of silicon substrates is generally performed for the purpose of removing particles and removing metal contamination.
Meanwhile, a surface of a silicon substrate is a plane which is intentionally inclined at about 0.2 to 0.5 degrees from a (100) plane. This is for preventing abnormal growth from occurring when an epitaxial layer is grown above the silicon substrate. Inclining a plane orientation of a surface from the (100) plane intentionally like this is sometimes called “giving an off-angle”
CZ (Czochralski) substrates for which epitaxial growth is not performed, and anneal substrates in which high temperature annealing is performed for the CZ substrates are also given the equivalent off-angles for production efficiency. Normally, the off-angle is given from the (100) plane to the <011> direction or the <011-> direction.
In recent years, with an improvement in integration, micronization of a semiconductor element advances, gate length is further being shrunk, and source/drain joint depth is being made shallower. As a result, carriers (electrons and holes) flowing through a channel under a gate electrode are transported in a portion nearer to a surface of a silicon substrate, and become sensitive to roughness of a surface of the silicon substrate. This is because irregularity on the surface causes scattering of the carriers, and carrier mobility is reduced by scattering. Consequently, it is desired that surface roughness in a channel region is low.
However, the roughness of the surface of the silicon substrate becomes high due to the aforementioned chemical solution treatment, and mobility of the carriers is reduced. Thus, in order to improve roughness of the surface of the silicon substrate, it is proposed to perform high temperature annealing in a vacuum, an H2 gas or an Ar gas. Further, to enhance mobility of the carriers, a manufacturing method of making steps existing on a substrate surface extend along a channel length direction is proposed.
Prior arts are disclosed in Patent Document 1 (Japanese Patent Laid-open No. 9-51097), Patent Document 2 (Japanese Patent Laid-open No. 2002-91342), Patent Document 3 (Japanese Patent Laid-open No. 10-326790), Patent Document 4 (Japanese Patent Laid-open No. 10-335659), Patent Document 5 (Japanese Patent Laid-open No. 8-264780), Patent Document 6 (Japanese Patent Laid-open No. 8-264401), Patent Document 7 (Japanese Patent Laid-open No. 8-264402), Patent Document 8 (Japanese Patent Laid-open No. 8-321443), Patent Document 9 (Japanese Patent Laid-open No. 5-347256), Patent Document 10 (Japanese Patent Laid-open No. 2002-151519), Patent Document 11 (Japanese Patent Laid-open No. 2002-3295), and Non-Patent Document 1 (H. Sayama et al., “Effect of <100> Channel Direction for High Performance SCE Immune pMOSFET with Less Than 0.15 μm Gate Length”, IEEE, 1999).
However, roughness cannot be sufficiently reduced by any of the methods and structures, and sufficient mobility of the carriers cannot be obtained.
The present invention is made in view of the above problems, and has its object to provide a manufacturing method of a semiconductor device capable of enhancing mobility of carriers by reducing roughness on a surface of a silicon substrate.